Well-known technoblogger Roman Hartung “Der8auer” decided to see for himself and show everyone that between the 14-nm transistors in Intel processors and 7-nm TSMC transistors in AMD processors is not as big a difference as we want to inspire marketers. Common sense says that the numbers “14” and “7” are twice as different, but in practice things are different for the technical processes.
As a test case, Der8auer has chosen the best that Intel and AMD currently have from mass PC products. He extracted samples with transistors from 14nm Intel Core i9-10900K (14+++ processor) and 7nm AMD Ryzen 9 3950X processor manufactured by TSMC Taiwan. As samples for study were selected sections of processors with second level cache memory. Transistors in the logic blocks have a spread of gates and ribs, while in the memory cells they are more or less the same and represent a regular (repeated) sequence convenient for comparison.
A study of each of the processor samples under the scanning electron microscope showed that 14nm Intel transistors have a 24nm wide gate, and 7nm AMD/TSMC transistors have 22nm wide gates (gate heights are also approximately the same). Neither 14 nor 7 nm is the case, as we can see. In justification of modern marketers, we can say that this discrepancy began after the technological process with the standards of 90 nm and accelerated after the transition from transistors with planar gates to vertical.
However, the 7-nm TSMC process was slightly better than Intel’s 14-nm process with the ability to place 90 million transistors on one square millimeter. In the case of 10nm Intel process, this company is a little ahead, because it promises to place 100.8 million transistors for each square millimeter. But this comparison also has its nuances.
So, three years ago for 10nm process Intel suggested not just to count transistors from one or another block on the processor, but to choose them purposefully and use weighting factors. For Intel metrics, transistors are taken from elementary logic. First, these are transistors from the two-input elements of NAND (not to be confused with NAND flash memory), which is assigned a weighting factor of 0.6. Secondly, transistors from triggers with a minimum of 25 gates are used, which is given a weighting factor of 0.4. From these data is derived transistor density, which, for example, as compared to the Der8auer, will be different from the real for the transistors in cache memory.
And again someone will have to take samples of processors, dissect them and literally manually read the real number of transistors. And so it will be until the industry agrees on a new metric, and if the marketing experts do not stick their nose in it.